[ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification


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File Size:   3.45 GB
Creat Time:   2024-05-26
Active Degree:   100
Last Active:   2024-11-18
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Tags:    CourseLala com Udemy - Verilog HDL Fundamentals for Digital Design and Verification
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File List

  1. ~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.mp4 115.65 MB
  2. ~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.mp4 111.37 MB
  3. ~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).mp4 105.51 MB
  4. ~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.mp4 79.88 MB
  5. ~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).mp4 71.67 MB
  6. ~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.mp4 60.81 MB
  7. ~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.mp4 52.20 MB
  8. ~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).mp4 52.08 MB
  9. ~Get Your Files Here !/1. Introduction/2. Course overview.mp4 51.70 MB
  10. ~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.mp4 51.08 MB
  11. ~Get Your Files Here !/1. Introduction/1. Welcome!.mp4 44.68 MB
  12. ~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.mp4 43.08 MB
  13. ~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.mp4 40.94 MB
  14. ~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.mp4 40.76 MB
  15. ~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.mp4 39.95 MB
  16. ~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.mp4 39.56 MB
  17. ~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.mp4 38.62 MB
  18. ~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.mp4 38.23 MB
  19. ~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.mp4 37.58 MB
  20. ~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.mp4 37.10 MB
  21. ~Get Your Files Here !/4. Verilog Module/1. Verilog Module - the basics.mp4 35.78 MB
  22. ~Get Your Files Here !/5. Verilog Design Styles/15. Action Time - 4bit_full_adder structural.mp4 34.89 MB
  23. ~Get Your Files Here !/11. Verilog State Machines/1. Discover Finite State Machines.mp4 34.76 MB
  24. ~Get Your Files Here !/8. Verilog Sequential Design/12. Action Time - Shift_Reg_SIPO.mp4 34.40 MB
  25. ~Get Your Files Here !/7. Verilog Combinational Design/23. Action Time - HEX 7segment decoder.mp4 33.00 MB
  26. ~Get Your Files Here !/8. Verilog Sequential Design/21. Action Time - Modulo_N Counter.mp4 32.88 MB
  27. ~Get Your Files Here !/11. Verilog State Machines/5. Action Time - Sequence Detector NON Overlaping.mp4 31.63 MB
  28. ~Get Your Files Here !/1. Introduction/4. Understand Abstraction Levels.mp4 31.36 MB
  29. ~Get Your Files Here !/8. Verilog Sequential Design/2. Action Time - Clocks Generator.mp4 29.89 MB
  30. ~Get Your Files Here !/4. Verilog Module/2. Action time - Do your first testbench.mp4 29.85 MB
  31. ~Get Your Files Here !/7. Verilog Combinational Design/21. Action Time - demux_4x_nbit.mp4 29.81 MB
  32. ~Get Your Files Here !/7. Verilog Combinational Design/13. Action Time - 4to16 binary Decoder.mp4 29.43 MB
  33. ~Get Your Files Here !/9. Verilog Functions and Tasks/7. Action Time - Nbit Comparator Function.mp4 28.89 MB
  34. ~Get Your Files Here !/11. Verilog State Machines/7. Verilog Mealy FSM Template.mp4 28.82 MB
  35. ~Get Your Files Here !/8. Verilog Sequential Design/6. Basics of edge-triggered logic.mp4 28.58 MB
  36. ~Get Your Files Here !/10. Verilog Memory Design/1. Basics of Semiconductor Memory.mp4 27.47 MB
  37. ~Get Your Files Here !/8. Verilog Sequential Design/11. Action Time - Shift_Reg_PIPO.mp4 26.44 MB
  38. ~Get Your Files Here !/12. Verilog Design Examples/4. Basics of Data Ecryption.mp4 26.24 MB
  39. ~Get Your Files Here !/8. Verilog Sequential Design/1. Sequential Logic Basics.mp4 26.05 MB
  40. ~Get Your Files Here !/7. Verilog Combinational Design/22. Master the Seven Segment Display Decoder.mp4 25.94 MB
  41. ~Get Your Files Here !/10. Verilog Memory Design/3. Action Time - Single Port Sync Read SRAM.mp4 25.37 MB
  42. ~Get Your Files Here !/8. Verilog Sequential Design/19. Action Time - Nbit Counter.mp4 24.00 MB
  43. ~Get Your Files Here !/7. Verilog Combinational Design/14. Action Time - 8to3 Encoder.mp4 23.92 MB
  44. ~Get Your Files Here !/12. Verilog Design Examples/1. Discover the First In First Out (FIFO) circuit.mp4 23.38 MB
  45. ~Get Your Files Here !/8. Verilog Sequential Design/23. Action Time - Clock Divider Nbit.mp4 23.26 MB
  46. ~Get Your Files Here !/7. Verilog Combinational Design/19. Action Time - mux_4x_nbit.mp4 23.22 MB
  47. ~Get Your Files Here !/7. Verilog Combinational Design/9. Action Time - Nbit Comparator.mp4 23.15 MB
  48. ~Get Your Files Here !/7. Verilog Combinational Design/11. Action Time - Nbit Decoder.mp4 23.04 MB
  49. ~Get Your Files Here !/3. Verilog Data Types and Operators/8. Action time - Vectors.mp4 23.00 MB
  50. ~Get Your Files Here !/5. Verilog Design Styles/3. Action Time - half adder structural.mp4 23.00 MB

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