[ DevCourseWeb.com ] Udemy - Verilog HDL programming with practical approach


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File Size:   2.89 GB
Creat Time:   2024-08-11
Active Degree:   7
Last Active:   2024-11-17
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File List

  1. ~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/001 Hamming code complete Design & TB for error detection & correction.mp4 218.86 MB
  2. ~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals.mp4 169.57 MB
  3. ~Get Your Files Here !/16 - Project 2 FIFO/008 Verilog HDL code for FIFO Test Bench.mp4 151.33 MB
  4. ~Get Your Files Here !/18 - FPGA/001 FPGA.mp4 134.85 MB
  5. ~Get Your Files Here !/13 - FSM/001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code.mp4 129.41 MB
  6. ~Get Your Files Here !/15 - Project 1 Memory controller/001 Memory controller with Design & TB.mp4 95.03 MB
  7. ~Get Your Files Here !/16 - Project 2 FIFO/007 Verilog HDL for FIFO design.mp4 91.56 MB
  8. ~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground.mp4 89.94 MB
  9. ~Get Your Files Here !/01 - Introduction to the course/001 Preview.mp4 86.62 MB
  10. ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC.mp4 82.04 MB
  11. ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC).mp4 78.37 MB
  12. ~Get Your Files Here !/12 - Functions & Task and system tasks/002 File based system tasks and random generator system task.mp4 70.14 MB
  13. ~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction.mp4 68.59 MB
  14. ~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/001 Sequence detector using FSM with complete Design & TB.mp4 66.60 MB
  15. ~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking.mp4 64.77 MB
  16. ~Get Your Files Here !/11 - Test bench/002 Example - Test bench for counter design.mp4 63.91 MB
  17. ~Get Your Files Here !/16 - Project 2 FIFO/009 Run the simulation and finding errors and Analyze the waveform Results.mp4 62.67 MB
  18. ~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always.mp4 62.54 MB
  19. ~Get Your Files Here !/11 - Test bench/003 Example - Test bench for Pulse generator.mp4 59.68 MB
  20. ~Get Your Files Here !/12 - Functions & Task and system tasks/001 Functions & tasks and system tasks.mp4 50.87 MB
  21. ~Get Your Files Here !/16 - Project 2 FIFO/005 Block Diagram and Architecture of FIFO.mp4 45.53 MB
  22. ~Get Your Files Here !/09 - Behavioral Modeling/009 Advantage of Non-blocking assignment Example Pipelining.mp4 39.35 MB
  23. ~Get Your Files Here !/09 - Behavioral Modeling/037 Example LFSR (Linear Feedback Shift Register).mp4 35.99 MB
  24. ~Get Your Files Here !/09 - Behavioral Modeling/011 Case – statement Example 4x1 Mux.mp4 34.87 MB
  25. ~Get Your Files Here !/04 - Three levels of verilog design Description/001 Three levels of verilog design Description.mp4 33.74 MB
  26. ~Get Your Files Here !/16 - Project 2 FIFO/002 Introduction to FIFO.mp4 33.21 MB
  27. ~Get Your Files Here !/09 - Behavioral Modeling/010 if-else statement Example 4x1 Mux.mp4 31.13 MB
  28. ~Get Your Files Here !/09 - Behavioral Modeling/031 Example UPDown Counter.mp4 28.03 MB
  29. ~Get Your Files Here !/11 - Test bench/001 Functional simulation.mp4 27.70 MB
  30. ~Get Your Files Here !/09 - Behavioral Modeling/038 memory design.mp4 27.67 MB
  31. ~Get Your Files Here !/16 - Project 2 FIFO/003 Write Read Operation of Normal RAM.mp4 27.60 MB
  32. ~Get Your Files Here !/13 - FSM/003 Example FSM- Divide by 3 clock.mp4 23.07 MB
  33. ~Get Your Files Here !/09 - Behavioral Modeling/030 Example Counter.mp4 19.90 MB
  34. ~Get Your Files Here !/12 - Functions & Task and system tasks/003 Read file and write in to memory system task.mp4 19.36 MB
  35. ~Get Your Files Here !/09 - Behavioral Modeling/033 Example Pulse Generator Mod-3 pulse generator.mp4 19.33 MB
  36. ~Get Your Files Here !/16 - Project 2 FIFO/006 Connection of FIFO design & Test bench environment.mp4 19.06 MB
  37. ~Get Your Files Here !/08 - Data flow modeling/009 Shift operators Leftright Shift.mp4 18.34 MB
  38. ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4 18.25 MB
  39. ~Get Your Files Here !/10 - Switch level modeling/001 Switch level modeling.mp4 18.11 MB
  40. ~Get Your Files Here !/09 - Behavioral Modeling/034 Example Divide by 3 clock.mp4 18.10 MB
  41. ~Get Your Files Here !/08 - Data flow modeling/002 Operators.mp4 17.63 MB
  42. ~Get Your Files Here !/09 - Behavioral Modeling/026 Example D Flip Flop vs D-Latch.mp4 17.51 MB
  43. ~Get Your Files Here !/09 - Behavioral Modeling/019 Example Full Adder & 4-bit Full Adder.mp4 17.45 MB
  44. ~Get Your Files Here !/09 - Behavioral Modeling/016 Example 8x1 Mux using 4x1 mux and 2x1 mux.mp4 17.28 MB
  45. ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/003 Compiler Directives.mp4 16.27 MB
  46. ~Get Your Files Here !/09 - Behavioral Modeling/002 Behavioral Modeling Constructs.mp4 15.79 MB
  47. ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4 14.84 MB
  48. ~Get Your Files Here !/09 - Behavioral Modeling/032 Example clock divider using counter- Divide by 2,4,8,.mp4 13.92 MB
  49. ~Get Your Files Here !/08 - Data flow modeling/011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4 13.91 MB
  50. ~Get Your Files Here !/12 - Functions & Task and system tasks/004 Programming Language Interface.mp4 13.81 MB